Conventional processors execute instructions from a program containing a sequence of instructions. Many conventional processors utilize control transfer instructions, such as branches, to allow the processor to vary the processing order of the instructions from the serial program sequence. Some control transfer instructions may be unconditional, causing a branch in all circumstances. Other control transfer instructions may be conditional, transferring the program flow upon a met condition, such as a result of an operation being equal to zero. The present invention operates with both unconditional as well as conditional control transfer instructions.
Control transfer instructions indicate a memory address from which the next logical instruction is to be read and executed. This address is known as the target address or the target. In the case of a conditional control transfer instruction, this next logical instruction at the target address is only processed if a condition indicated by the instruction is met, otherwise the next physical instruction is used as the next logical instruction.
The control transfer instruction may indicate the target address in a variety of ways. In some conventional processors, the instruction contains the complete target address. Such control transfer instructions are referred to as "absolute." Such control transfer instructions execute rapidly because the entire address is available within the instruction, although the instruction length can be large.
Other control transfer instructions indicate the target address using an instruction displacement field relating to the memory address of the control transfer instruction itself. The memory address of the control transfer instruction may be the address of the first word of the instruction, although any memory address related in some fashion to the instruction may be used. The displacement, which may be positive or negative, is added to the memory address of the control transfer instruction to produce the target address. Such control transfer instructions are referred to as "relative." Because many target addresses are near the address of the control transfer instruction, the use of relative control transfer instructions can result in substantial instruction length savings. However, the use of relative control transfer instructions can slow the execution of the instructions because the processor must first add the displacement to the address of the control transfer instruction to produce the target address.
One conventional technique used to speed the execution of relative control transfer instructions has been to utilize faster adders to compute the target address when the control transfer instruction is executed. However, the use of faster adders may not be able to achieve a desired speed of execution.
Another conventional technique has been to precompute the target address in advance of the execution of the control transfer instruction. While this technique optimizes the speed of execution, it can dramatically increase the size of storage required to store the control transfer instruction and can increase the size of the data paths required to deliver relative control transfer instructions to the unit which will execute the instruction.
Another conventional technique has been to predict the target address by storing the most recent set of target addresses from other executed control transfer instructions, under the theory that target addresses from several control transfer instructions are often the same. Such a technique requires additional storage to store previous target addresses, and can incur additional processor time if the predicted target is incorrect.